1. Technical Field
The present invention relates to a semiconductor apparatus, and more particularly, to a semiconductor apparatus and a calibration method thereof.
2. Related Art
Semiconductor apparatuses, specifically memory apparatuses such as a dynamic random access memory (DRAM), are constantly required to be reduced in size and increased in capacity and performance. Accordingly, memory apparatuses are highly integrated and it is necessary to increase the capacity of a unit package to meet this requirement. From this need, technologies have been developed which increase the capacity of semiconductor apparatuses while packaging a plurality of chips into a single package. Furthermore, recent studies have been extensively conducted on three-dimensional (3D) package semiconductor apparatuses using a Through Silicon Via (TSV) technology in which a via passes through a plurality of stacked chips so that they can be electrically connected together.
The plurality of chips contained in a single package operates as a single semiconductor apparatus. Thus, characteristics of the respective chips with respect to process, voltage and temperature (PVT) variations must coincide with one another. However, due to constraints imposed by semiconductor fabrication processes for fabricating a large number of chips on a wafer, the stacked chips constituting a single semiconductor apparatus inevitably have varied characteristics from one another.